O HAI THIS BLOG PURPZIEZ 2 B UZED AZ MAH PLESIOUS MEM. :)

2007/09/03

IfGenerateStatement.karma--;

仕様なのは知ってるけど,VHDLのif-generateはなんでelseが使えないんだ? :(
[VHDL's if-generate statement kinda sux. :(]
:
:
entity FOO is
generic (
:
nDW : integer 3 to integer'high := 12;
nDELAY : integer 0 to integer'high := 2**8 - 1;
nNL : integer 3 to integer'high := 2**4 - 1;
:
);
port (
:
iCLR : in std_logic;
iDIN : in std_logic_vector(nDW-1 downto 0);
oDOUT : out std_logic_vector(nDW-1 downto 0);
:
);
end FOO;
:
architecture RTL of FOO is
:
:
constant cZEROxDW : std_logic_vector(nDW-1 downto 0) := (others => '0');
type tDMEM is array (0 to nNL-2) of std_logic_vector(nDW-1 downto 0);
signal rDMEM : tDMEM := (others => cZEROxDW);
:
:
begin
:
:
G_0FF_DELAY : if (nDELAY = 0) generate
oDOUT <= cZEROxDW when (iCLR = '1') else iDIN;
end generate;

G_1FF_DELAY : if (nDELAY = 1) generate
P_1FF_DELAY : process (iCLK)
if (iCLK'event and iCLK = '1') then
if (iCLR = '1') then
oDOUT <= cZEROxDW;
else
oDOUT <= iDIN;
end if;
end if;
end process;
end generate;

G_nFF_DELAY : if (nDELAY > 1) generate
P_nFF_DELAY : process (iCLK)
if (iCLK'event and iCLK = '1') then
nADDR <= (nADDR + 1) mod (nNL - 1)
if (iCLR = '1') then
for v in rDMEM'range loop
rDMEM(v) <= cZEROxDW;
end loop;
oDOUT <= cZEROxDW;
else
rDMEM(nADDR) <= iDIN;
oDOUT <= rDMEM(nADDR);
end if;
end if;
end process;
end generate;
:
:
end RTL;
それからModelSim XE 6.2gがこうやって書くとmultiple sourcesだと勘違いしやがる.
coverage機能がどうのこうのと言う前に嘘の警告を出さない様にしてくれ. :P
[And ModelSim XE 6.2g also sux, it'd buzz me about this code has multiple
sources, WTF. To fix wrong buzz should be given priority over to improve
coverage features, IMHO. :p]

修正: "type tDMEM us" -> "type tDMEM is"
[FIX: "type tDMEM us" -> "type tDMEM is"]

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